1. Field of the Invention
The invention relates to Integrated Circuits in which complementary metal-oxide semiconductor (CMOS) logic is combined with Bi-polar devices and/or double diffused MOS (DMOS) power devices (i.e. BiMOS ICs) and more particularly to Radiation Tolerant Complementary MOS Logic for BiMOS Integrated Circuits.
2. Prior Art
IC technology which is capable of integrating complementary power DMOS output devices with high performance Bi-polar CMOS analog and digital components has recently been developed and successfully applied in a variety of applications. While this technology offers substantial performance improvements compared to implementations using conventional IC's, discretes, or hybrid designs, the on-chip CMOS logic limits its usefulness for applications which must meet tatical total dose gamma radiation requirements.
Requirements for military avionic control systems often include a total dose radiation specification. While the Power BiMOS IC technology offers unique advantages in the development of interface IC's, the polysilicon gate CMOS devices are not radiation tolerant. The principal effects of radiation in MOS devices are changes in the threshold voltage, flatband voltage and channel mobility due to trapped charge in the gate insulator. Radiation-induced threshold shift is the prime concern in the operation of CMOS devices. For both PMOS and NMOS transistors, radiation causes the threshold voltage to shift toward more negative values. The PMOS transistor becomes harder to turn-on. Conversely, the NMOS threshold shifts towards becoming a depletion mode device where it is permanently turned-on. The physical phenomena for this behavior is that radiation produces electron-hole pairs in the SiO.sub.2 gate insulator. A fraction of the holes become trapped in the SiO.sub.2, as the various gate induced fields sweep out the electrons as part of normal circuit operation. The trapped positive charge build-up in the SiO.sub.2 gate layer adjacent to the channel causes the threshold to shift toward more negative gate voltages. This effect is accentuated by the fact that, in the NMOS transistor the trapped charges migrate toward the silicon-insulator interface, but in the PMOS transistor they migrate toward the polysilicon gate. Hence the PMOS transistor is inherently more radiation-resistant than the NMOS for this reason. Conventional NMOS devices typically fail at 1 krad (Si) with the upper limit for safe operation at 1-3 krads. Several techniques have been developed to extend the radiation tolerance of silicon-based CMOS, these include the use of aluminum gates, minimizing the gate oxide thickness, ion implantation techniques, and fixed well potentials. These methods are not easily adaptable to the Power BiMOS technology since most require fundamental processing changes which would jeopardize the performance of the Bi-polar and DMOS devices.